1. Technical Field
This invention relates generally to a method and apparatus for testing semiconductor chip devices and, more particularly, to a method and apparatus for verifying the connectivity of chip-to-package input/outputs (I/Os) on a high speed semiconductor chip having a common I/O, also known as bidirectional I/O (BIDI).
2. Background Art
In the testing of semiconductor chip devices, such as application specific integrated circuits (ASICs) and/or microprocessors with high speed I/Os, a variety of tests are performed to ensure proper functionality and connectivity. These tests may include, for example, time interval tests for particular semiconductor chip functions (i.e. access, setup, and hold times), and connectivity tests to determine the connectivity of a semiconductor device chip to the semiconductor device package. Conventionally, testing of a semiconductor device requires a direct connection by test equipment to each package I/O to complete all necessary tests.
With conventional semiconductor chip testing technology, time intervals are measured by a tester external to the semiconductor chip, wherein the tester provides appropriate testing signals and measures corresponding response times for a particular tested function. The particular semiconductor chip device is then characterized and classified based upon the measured response time. Testing of semiconductor chip I/Os has historically been performed with a physical tester/DUT (device under test) interface and an appropriate set of test signal patterns, waveforms, and timings created by a tester in accordance with a particular semiconductor device or chip testing procedure.
U.S. Pat. No. 6,058,496 to Gillis et al. (May 2, 2000) (hereinafter sometimes referred to as “Gillis”), the disclosure of which is hereby incorporated herein by reference, is assigned with the present invention to a common assignee. Gillis discloses a SELF TIMED AC CIO WRAP METHOD AND APPARATUS for testing a semiconductor chip. The invention of Gillis relates to a semiconductor chip with a common or bidirectional I/O pad which is electrically coupled to an off-chip driver and an off-chip receiver associated with a tester. A common I/O refers to a type of semiconductor device I/O which has both a driver and a receiver connected to the same physical pad on the device. FIG. 2 of Gillis is included as FIG. 1 herein. As shown in FIG. 1 herein, Gillis discloses and describes an invention which includes an external tester-generated launch clock 90 and a capture clock 92 which are used in AC CIO Wrap delay fault testing. The Gillis invention also includes tester drivers 102 and 104, fixturing 106 and 108, a semiconductor device pad C-4, a launch latch 112, an observation latch 114, a clock tree 100, a semiconductor chip driver 94 and a semiconductor chip receiver 96.
For the AC CIO Wrap testing method for the device shown in FIG. 1, the tester launches or triggers a “rising” or “falling” edge which propagates through the I/O to check for AC delay defects in the I/O. An “error” in the measurement is characterized by tester driver skew plus the error in the on-chip clock tree 100 fanout. The tester is not coupled to the output C-4 pad of the CIO being tested. Clock trees are shown in the FIG. to indicate that there can be a fanout of clocks and clock signals. The clocks from the clock trees may couple to multiple latches on the chip other than those shown. With LSSD (Level Sensitive Scan Delay), one clock tree feeds the L1 latches and a different clock tree feeds the L2 latches. In this way, the timing of I/Os may be tested without directly coupling a test probe to every I/O.
Conventional semiconductor device testing methods, including those disclosed in Gillis, however, do not provide a means by which a semiconductor device may be tested for package connectivity on the same testing equipment that other testing is performed. Under conventional methods, each semiconductor device must be tested for chip-to-package connectivity using separate testing equipment with test probes directly coupled to and testing each package I/O. Transfer of the semiconductor device to new testing equipment and testing each individual I/O requires additional time and cost in the testing process.
It would thus be desirable to provide a method and apparatus for verifying package connectivity for a semiconductor device which does not require transfer to additional testing equipment or connection to each individual package I/O.